With development of electronic devices in recent years, size reduction, higher performance, and the like are demanded in the semiconductor device employed in the electronic devices. In order to respond to the demands, the semiconductor device which has such a structure that semiconductor chips, etc. are stacked have already been put in practical use.
In one example of such semiconductor devices, the upper wiring substrate having the solder electrodes is arranged on the lower wiring substrate on which the semiconductor chip is mounted, and then both the lower wiring substrate and the upper wiring substrate are connected electrically via the solder electrodes by the reflow heating.
A related art is disclosed in Japanese Laid-open Patent Publication No. 2007-288228.
As explained in the column of the preliminary matter described later, in the electronic device manufacturing methods, there is a method that a plurality of upper substrates are soldered onto a plane of a sheet of lower substrate by sequentially applying the reflow heating. In this method, when the second upper substrate is connected to the lower substrate, in order to prevent such an event that solder electrodes of the first upper substrate which is already mounted are reflowed again, it is necessary that a temperature of the stage is set considerably lower than a reflow temperature.
Owing to this temperature difference, strong thermal stress is caused between the lower substrate and the upper substrate by a difference of thermal expansion. As a result, there exist such problems that warping of the substrate is ready to occur, and that sufficient reliability of the electrical connection cannot be obtained.